IEEE ICRC 2022 Keynote Speakers


IEEE ICRC 2022 Special Session: Logic Synthesis for Low-Temperature Electronics


IEEE ICRC 2022 Keynote Speakers

Prof. Sayeef Salahuddin, TSMC Distinguished Professor of Electrical Engineering and Computer Sciences at the University of California Berkeley

Sayeef Salahuddin

Talk Title: CMOS+X: Integrated Ferroelectric Devices for Energy Efficient Electronics

Talk Abstract: The last decade the computational throughput has increased by orders of magnitude over the last decade. Energy efficiency is critical not only to maintain this incessant advancement, but also to ensure that electronics does not become a drag on the finite energy resources of the world. This will need a radical rethinking of the basic building blocks that constitute the electronic hardware. In this talk, I shall briefly present how integrated ferroelectric devices offer a new pathway in this context. First, I shall discuss the phenomenon of negative capacitance in ferroelectric materials. A fundamentally new state in the ferroelectrics, negative capacitance promises to reduce power consumption in electronic devices significantly. I shall discuss our current understanding of negative capacitance derived from numerous experimental works done over the last few years. We shall further discuss the material science that is enabling the integration of negative capacitance into advanced transistors. Going beyond transistors, the insight gained from physics and materials could also lead to advanced, low power memory devices. These examples underscore how functional augmentation of CMOS by harnessing new physical phenomena, we are calling it CMOS+X, could offer opportunities that are otherwise not available through conventional means.

Bio: S. Salahuddin is the TSMC Distinguished Professor of Electrical Engineering and Computer Sciences at the University of California Berkeley. His group explores physics for low power electronic and spintronic devices. He is mostly known for the discovery of the Negative Capacitance effect that shows substantial promise for logic, memory and energy storage devices. Salahuddin received the Presidential Early Career Award for Scientist and Engineers (PECASE) from President Obama. Salahuddin also received several other awards including the National Science Foundation CAREER award, the IEEE Nanotechnology Early Career Award, the Young Investigator Awards from the Airforce Office of Scientific Research and the Army Research Office, and the IEEE George E Smith Award. Salahuddin is a co-director of the Berkeley Device Modeling Center (BDMC) and Berkeley Center for Negative Capacitance Transistors (BCNCT). Salahuddin is also a co-director of ASCENT, which is a flagship device technology effort in the US, jointly supported by SRC and DARPA. He served on the editorial board of IEEE Electron Devices Letters (2013-16) and was the chair the IEEE Electron Devices Society committee on Nanotechnology (2014-16). Salahuddin is a Fellow of the IEEE and the APS.


Dr. D. Scott Holmes, Booz Allen Hamilton

D. Scott Holmes

Talk Title: Superconducting quantum computing technology roadmap: First cut

Talk Abstract: Superconducting circuits are a promising approach to quantum computing. Both IBM and Google have presented timelines with goals of one million physical superconducting qubits by 2026 to 2029. Key technologies to achieve this goal include physical qubits with sufficiently low error rates, an efficient error-correction scheme, error-corrected logical qubits, and control systems that don’t exceed available refrigeration capacity. A roadmap for the key technologies is presented and assessed for feasibility.

Bio: Dr. D. Scott Holmes chairs the Cryogenic Electronics and Quantum Information Processing (CEQIP) International Focus Team (IFT) for the International Roadmap for Devices and Systems (IRDS). He supports the Intelligence Advanced Research Projects Agency (IARPA), including the SuperTools program to develop electronic design automation (EDA) tools for superconductor circuits and the Cryogenic Computing Complexity (C3) program that developed technologies for energy-efficient superconductor computing. He served as a DARPA program manager in the Microsystems Technology Office (MTO). Earlier career experience includes large-scale superconductor systems development at what is now the Air Force Research Laboratory, Lake Shore Cryotronics, and a decade as a Learning Strategist. Areas of interest include superconductor electronics and novel computing technologies. Professionally, Holmes is a member of the IEEE Council on Superconductivity as a representative of the Electron Device Society. Holmes received a BSME from MIT and graduate degrees from the University of Wisconsin–Madison.


IEEE ICRC 2022 Special Session: Logic Synthesis for Low-Temperature Electronics
Chaired By: P.-E. Gaillardon, University of Utah


Dr. Leon Stok, IBM

Talk Title: EDA for Quantum Computing and QC for EDA.

Talk Abstract: Though early in its development, quantum computing is now available on real hardware via the cloud through IBM Quantum. This radically new kind of computing holds open the possibility of solving some problems that are now and perhaps always will be intractable for “classical” computers.

As with any new technology there are a lot of open questions. What is the road to the point where quantum computing shows demonstrable and significant advantage over classical computers and algorithms on real world problems? What is the status of Quantum computers today? How do we define system-metrics to measure the performance of a Quantum System? We will discuss how EDA is helping to advance quantum computing and what EDA problems could potentially be more tractable by Quantum Computing. This lecture will answer several of these questions.

Bio: Leon Stok is Vice President of IBM’s Electronic Design Automation group. His team delivers world- class design and verification flows and tools being used to design the world’s largest supercomputers, IBM Z and Power systems and IBM Quantum Systems. Prior to this he held positions as director of EDA and executive assistant to IBM’s Senior Vice President of Technology and Intellectual Property and executive assistant to IBM’s Senior Vice President of the Technology group. Leon Stok studied electrical engineering at Eindhoven University of Technology, the Netherlands, from which he graduated with honors in 1986. He obtained a Ph.D. degree from Eindhoven University in 1991. At IBM’s Thomas J. Watson Research Center, Leon Stok pioneered logic synthesis, as part of the team that developed BooleDozer. Subsequently he managed IBM’s synthesis group and drove the first commercial application of physical synthesis bt developing, IBM’s Placement Driven Synthesis tool. From 1999-2004 he led all of IBM’s design automation research as the Senior Manager Design Automation at IBM Research. He drove key innovations in DFM using RRR (Radically Restrictive Rules), in static timing analysis using statistical timing and in large block physical synthesis. Dr. Stok has presented over forty keynotes, invited talks and tutorials at major IEEE and ACM conferences worldwide and at many leading universities. Dr. Stok has published over sixty papers on many aspects of high level, architectural and logic synthesis, low power design, placement driven synthesis and on the automatic placement and routing for schematic diagrams. He holds 13 patents in EDA. He was elected an IEEE fellow for the development and application of high-level and logic synthesis algorithms.


Dr. Mathias Soeken, Microsoft

Talk Title: How many qubits do you need, really?

Talk Abstract: While quantum computers promise to solve some of the scientifically and commercially valuable problems intractable for classical machines, delivering on this promise will require a large-scale quantum machine integrated with the cloud. Determining how to best navigate the architecture design choices of a large-scale quantum computer that efficiently caters to the performance and quality requirements of practical applications is an open challenge. To this end, we have developed Azure Quantum Resource Estimation, a tool which uses detailed models of the quantum stack to provide resource estimates (such as qubit counts and runtimes) for large-scale algorithms. Understanding the number of qubits required for a quantum program and the differences between qubit technologies allows innovators to prepare and refine their quantum programs to run on future scaled quantum machines and ultimately accelerate their quantum impact. In the talk, we will illustrate the framework that we apply to perform resource estimation and demonstrate how the tool helps to analyze resource requirements for scalable quantum algorithms. You’ll leave ready to find out just how many qubits you’ll need, really.

Bio: Mathias Soeken works at the Azure Quantum team at Microsoft. From 2015 to 2020, he has been with École Polytechnique Fédérale Lausanne (EPFL), Switzerland as postdoctoral scientist. He holds a Ph.D. degree (Dr.-Ing.) in Computer Science from University of Bremen, Germany (2013). His research interests are logic synthesis, quantum computing, reversible logic, and formal verification.


Dr. Luca Amaru, Synopsys

Talk Title: An Automated RTL-to-GDSII Flow for Single Flux Quantum Circuits Based on Industrial CMOS Tools

Talk Abstract: Josephson Junction-based superconducting circuits are promising candidates for high-speed digital electronics with dramatically lower power consumption than CMOS, as well as a potential enabler in research towards the implementation of large-scale quantum computing. In this presentation, we will describe an automated industrial flow for the creation of microcontrollers and other digital systems in the Single Flux Quantum (SFQ) technology. Starting with a Register-Transfer Level (RTL) description of the circuit, the flow integrates logic synthesis, technology mapping, timing and logic verification, library cell placement and routing, and completes with a physical design for fabrication. We will examine the challenges specific to superconducting electronics (SCE) technology at the different stages in this flow and report on the implementation results.

Bio: Luca Amaru is Principal R&D Engineer in the Silicon Realization Group of Synopsys Inc., Sunnyvale, CA, USA. He is responsible for designing the next generation of logic optimization and synthesis technologies. When not coding, Dr. Amaru leads an exceptional team of R&D engineers focusing on logic synthesis. Previously, he was research assistant at EPFL, Integrated Systems Laboratory, Lausanne, Switzerland (2011-2015), and visiting researcher at Stanford University, Palo Alto, CA, USA (2014). Dr. Amaru received his PhD degree in Computer Science from EPFL, Lausanne, Switzerland (2015). He received his double Master’s Degree in Electronic Engineering, with honors, from Politecnico di Torino, Turin, Italy, and Politecnico di Milano, Milan, Italy (2011). He received his Bachelor’s Degree in Electronic Engineering, with honors, from Politecnico di Torino, Turin, Italy (2009). At present, Dr. Amaru is author or coauthor of 104 scientific articles and inventor or coinventor of 15 patents.